A conventional solid state image sensor will now be described with reference to the drawings. FIG. 20 shows an example of the configuration of a conventional interline transfer solid-state image pickup device.
As shown in FIG. 20, a solid-state image pickup device 100 includes, on a substrate, photodiodes (light receiving units) 101, readout gates 102, vertical registers 103, a horizontal register 104, and a floating diffusion layer charge detecting unit 105.
The two-dimensionally arranged photodiodes 101 photoelectrically convert incident light and accumulate a signal charge whose amount corresponds to the amount of incident light. The readout gates 102 read out the signal charge accumulated in the photodiodes 101 to the vertical registers 103. The vertical registers 103 transfer the signal charge received from the photodiodes 101 via the readout gates 102 in a vertical direction (first direction). The horizontal register 104 transfers the signal charge received from the vertical registers 103 in a horizontal direction (second direction) that is perpendicular to the aforementioned vertical direction. The charge detecting unit 105 provided on one end of the horizontal register 104 converts the signal charge received from the horizontal register 104 into a voltage signal. Hereinafter, an example involving a four-phase drive vertical register and a two-phase drive horizontal register will be described.
Subsequently, operations of a conventional solid state image sensor including the aforementioned solid-state image pickup device 100 will be briefly described.
First, the solid state image sensor causes light to be incident on the photodiode 101 for any interval. The photodiode 101 converts the incident light into a signal charge whose amount corresponds to the amount of incident light and accumulates the converted signal charge.
The solid state image sensor then turns on the readout gate 102 during a vertical blanking interval. The readout gate 102 that is now turned on sends the signal charge accumulated in the photodiode 101 to the vertical register 103.
Next, the solid state image sensor drives the vertical register 103 by vertical drive pulses φV1 to φV4 during a horizontal blanking interval. The vertical register 103 driven by the vertical drive pulses φV1 to φV4 performs a vertical-direction single stage transfer of the signal charge received from the readout gate 102. At this point, a signal charge existing in the final stage of the vertical register 103 is transferred to the horizontal register 104.
The solid state image sensor then drives the horizontal register 104 with horizontal drive pulses φH1 and φH2 during an effective interval. The horizontal register 104 driven by the horizontal drive pulses φH1 and φH2 transfers the signal charge received from the vertical register 103 in a horizontal direction and sends the signal charge to the charge detecting unit 105.
The charge detecting unit 105 converts the signal charge received from the horizontal register 104 into a voltage signal and outputs the converted voltage signal to the outside of the solid-state image pickup device 100.
FIG. 21 shows a part of a circuit of a conventional solid state image sensor. As shown in FIG. 21, the solid state image sensor includes a clock generator 1, a horizontal driver power supply unit 2, a first horizontal drive circuit 3, and a second horizontal drive circuit 4.
The clock generator 1 includes a logic circuit which generates clock pulses H1 and H2 having required periods and required amplitudes. The horizontal driver power supply unit 2 includes a power supplying terminal to be connected to the first horizontal drive circuit 3 and a power supplying terminal to be connected to the second horizontal drive circuit 4, and generates power to be supplied to the horizontal drive circuits 3 and 4.
The first horizontal drive circuit 3 generates a horizontal drive pulse φH1 based on a clock pulse H1. The second horizontal drive circuit 4 generates a horizontal drive pulse φH2 based on a clock pulse H2. The two horizontal drive circuits 3 and 4 are formed on the same circuit board (the same chip) 5.
Additionally, in FIG. 21, reference character L1 denotes a reactance component parasitic on a wire (power supply line) connecting the power supplying terminal of the horizontal driver power supply unit 2 and the power terminal of the first horizontal drive circuit 3. Furthermore, reference character L2 denotes a reactance component parasitic on a wire (power supply line) connecting the power supplying terminal of the horizontal driver power supply unit 2 and the power terminal of the horizontal drive circuit 4. Moreover, reference character IH1 denotes a current flowing from the horizontal driver power supply unit 2 to the first horizontal drive circuit 3. In addition, reference character IH2 denotes a current flowing from the horizontal driver power supply unit 2 to the second horizontal drive circuit 4.
FIG. 22 shows the configuration of the junction of the aforementioned vertical register 103 and the horizontal register 104. As shown in FIG. 22, the vertical register includes a transfer channel 201 and transfer electrodes 202 to 205. In addition, the horizontal register includes a transfer channel 206 and transfer electrodes 207 to 210.
Vertical drive pulses φV1 to φV4 are respectively applied to the transfer electrodes 202 to 205 of the vertical register. A potential barrier (not shown) is formed under the transfer electrodes 207 and 209 of the horizontal register. In addition, a horizontal drive pulse φH1 is applied to the transfer electrodes 207 and 208 of the horizontal register. A horizontal drive pulse φH2 is applied to the transfer electrodes 209 and 210 of the horizontal register.
FIG. 23 shows examples of signal waveforms of the horizontal drive pulses φH1 and φH2 generated by the first and second horizontal drive circuits 3 and 4, signal waveforms of the currents IH1 and IH2 flowing from the horizontal driver power supply unit 2 to the first and second horizontal drive circuits 3 and 4, and waveforms of a voltage (terminal voltage) applied to the power terminals of the first and second horizontal drive circuits 3 and 4. In addition, FIG. 24 shows an enlarged view of a portion A of the signal waveforms of the horizontal drive pulses φH1 and φH2 shown in FIG. 23.
As shown in FIG. 23, the horizontal drive pulses φH1 and φH2 are pulses that are in opposite phases to each other and normally have a low level of 0V and a high level of 3 to 5 V.
In addition, during a horizontal blanking interval, the horizontal drive pulse φH1 applied to the transfer electrodes 207 and 208 of the horizontal register is suspended in a high-level state and the horizontal drive pulse φH2 applied to the transfer electrodes 209 and 210 of the horizontal register is suspended in a low-level state. During the horizontal blanking interval, a signal charge existing in the final stage of the transfer channel 201 of the vertical register is transferred to under the transfer electrode 208 of the horizontal register.
After the horizontal blanking interval, the signal charge transferred to under the transfer electrode 208 of the horizontal register is transferred through the transfer channel 206 of the horizontal register by the horizontal drive pulses φH1 and φH2 in opposite phases to each other and is converted into a voltage signal at the charge detecting unit 105.
As described above, in the conventional solid state image sensor, horizontal drive pulses φH1 and φH2 which regulate the drive timing of the horizontal register are suspended in a horizontal blanking interval (refer to Patent Document 1).
However, in the conventional solid state image sensor, as shown in FIG. 23, while a current periodically flows from the horizontal driver power supply unit to the horizontal drive circuit during an effective interval in which a signal charge is transferred from the horizontal register to the charge detecting unit, hardly any current flows from the horizontal driver power supply unit to the horizontal drive circuit during a horizontal blanking interval. Consequently, a large current rapidly flows out from the horizontal driver power supply unit immediately after the start of an effective interval. Such a current variation generates a power supply ripple due to the influence of a reactance component parasitic on the power supply line connected to the horizontal driver power supply unit even when the voltage at the power supplying terminal of the horizontal driver power supply unit is constant. Therefore, immediately after the start of an effective interval, a ripple as shown in FIG. 23 is generated on a voltage (terminal voltage) applied to the power terminals of the horizontal drive circuits 3 and 4. Consequently, as shown in FIG. 24, the generation of the power supply ripple disturbs the phases of the horizontal drive pulses φH1 and φH2 immediately after the start of the effective interval by approximately several tens of bits.
As shown, disturbances in the phases of the horizontal drive pulses φH1 and φH2 immediately after the start of an effective interval cause image degradation. This image degradation will now be described with reference to FIGS. 25 and 26.
FIG. 25 is a schematic diagram of a voltage signal generated at a charge detecting unit of a conventional solid state image sensor. FIG. 26 is a schematic diagram showing a conventional image.
When disturbances in the phases of the horizontal drive pulses φH1 and φH2 occur immediately after the start of an effective interval, as shown in FIG. 25, the signal level of a voltage signal generated at the charge detecting unit 105 drops immediately after the start of the effective interval. Subsequently, as the signal level of the voltage signal generated at the charge detecting unit 105 drops immediately after the start of the effective interval, as shown in FIG. 26, image degradation such as shading or ringing occurs in an image portion along the left edge of a screen.
As shown, in the conventional solid state image sensor, a power supply ripple generated immediately after the start of an effective interval disadvantageously causes image degradation such as shading or ringing in an image portion along the left edge of a screen.
A power supply ripple can conceivably be prevented from occurring immediately after the start of the effective interval either by connecting a large-capacity capacitor to each power supplying terminal of the horizontal driver power supply unit in order to cancel the reactance components parasitic on the wires (power supply lines) connecting the power supplying terminals of the horizontal driver power supply unit with the power terminal of the horizontal drive circuit or by minimizing the lengths of the power supply lines in order to minimize the reactance components parasitic on the power supply lines. However, such measures may not be sufficiently implemented in some camera systems due to mounting restraints and therefore cannot be considered effective.    Patent Document 1: Japanese Patent Laid-Open No. 2004-229058
In consideration of the disadvantage described above, an object of the present invention is to provide a solid state image sensor capable of preventing a power supply ripple from being generated immediately after the start of an effective interval and preventing image degradation such as shading or ringing from occurring in an image portion along the left edge of a screen, by causing a current to be generated at a horizontal driver power supply unit during an interval in which a horizontal drive pulse is suspended (a horizontal blanking interval).